1. Field of the Invention
The present invention relates to a circuit arrangement for variably adjustable time delay of digital signals comprising a matrix-shaped memory arrangement.
2. Description of the Prior Art
Facilities for providing defined time delays of digital data streams are frequently required in the field of digital signal processing, as well as in the field of communications technology. Defined time delays are employed, for example, for the compensation of transit times. Given a constant number of desired delay clocks, an arrangement comprising a shift register is generally available as a time delay device. When, however, the time delay is to be variably adjustable, then particular problems arise given the use of shift registers.
It is also known in the art to delay data streams using an arrangement composed of standard circuits and memory modules. In such an arrangement, the components of the data stream are deposited in a freely addressable memory. This memory is driven by a decoder which is, in turn, driven by one (or more) counters. The duration of the time delay is thereby established by the spacing of the counter reset pulses. Since the memory cells of such freely addressable memories can only read or write, respectively, per clock, the necessity thereby arises of either operating the memories with twice the clock rate or switching back and forth between two memory units in a multiplex mode. The first solution of this problem is the disadvantage that the maximum data clock frequency can only be half as high as the maximum memory cycle frequency. The latter requires involved logic circuits for address control and a required reordering of the data. Disadvantages also arise for integration of such a circuit arrangement because of the high space requirement of the required multiplexers and because of the extensive wiring required.